Platform-level interrupt controller (PLIC)

The PLIC is a RISC-V interrupt controller and specifically we are using OpenTitan's interrupt controller. Please find more details in the official specification. Part of these details are is the memory map, which shows all registers from the base until base + 0x3FFFFFC. Not all of these registers are mapped, most importantly we only have one core, so only one context (context 0).

The following table shows the current list of interrupts that are fed through the PLIC. For more detailed descriptions of what each interrupt means, please refer to the documentation of each individual hardware IP block. More interrupts may be added to this table in the future.

NumberBlockInterrupt description
0NoneTied to zero
1, 9UART 0, 1Transmit watermark
2, 10UART 0, 1Receive watermark
3, 11UART 0, 1Transmit empty
4, 12UART 0, 1Receive overflow
5, 13UART 0, 1Receive frame error
6, 14UART 0, 1Receive break error
7, 15UART 0, 1Receive timeout
8, 16UART 0, 1Receive parity error
17, 32I2C 0, 1Format FIFO threshold
18, 33I2C 0, 1Receive FIFO threshold
19, 34I2C 0, 1Acquire FIFO threshold
20, 35I2C 0, 1Receive FIFO overflow
21, 36I2C 0, 1Received NACK
22, 37I2C 0, 1SCL interference
23, 38I2C 0, 1SDA interference
24, 39I2C 0, 1Stretch timeout
25, 40I2C 0, 1SDA unstable
26, 41I2C 0, 1Command complete
27, 42I2C 0, 1Transmit stretch
28, 43I2C 0, 1Transmit threshold
29, 44I2C 0, 1Acquire FIFO full
30, 45I2C 0, 1Unexpected stop
31, 46I2C 0, 1Host timeout
47EthernetInterrupt from external SPI ethernet chip (KSZ8851SNLI-TR). Check the interrupt status register for details.